Synthesis of FSMs on the Basis of Reusable Hardware Templates

This paper suggests a reusable hardware template (HT) for finite state machines (FSM) and a method for the synthesis of FSMs based on such a template. The HT is a circuit with a predefined structure that has already been implemented in hardware (for example, in FPGA). By reprogramming its RAM-blocks we can implement a different functionality of the FSM. The proposed method permits the translation of a given FSM specification (that takes into account the parameters of a particular HT) into bitstreams for reloading the RAMblocks. Run-time modifications are also permitted with the aid of dual-port memory. Note that the resulting FSM circuits are very fast and any state transition is performed within one clock cycle. The designed C++ program provides synthesis, verification and modeling of FSMs. The synthesized circuits were implemented and tested in Xilinx FPGAs. The synthesis methods considered permit various target requirements to be satisfied, such as minimizing the complexity of the circuit and the possibility for changes in the circuit functionality. Key-Words: Finite State Machine, Hardware Template, Logic Synthesis, FPGA